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1. general description the dac1205d750 is a high-speed 12-bit dual channel digital-to-analog converter (dac) with selectable 4 ? or 8 ? interpolating filters optimized for multi-carrier wireless transmitters. thanks to its digital on-chip modulation, the dac1205d750 allows the complex i and q inputs to be converted from baseband (bb) to if. the mixing frequency is adjusted via a serial peripheral inte rface (spi) with a 32-bit numerically controlled oscillator (nco) and the phase is controlled by a 16-bit register. two modes of operation are available: separate data ports or a single interleaved high-speed data port. in the interleaved mode, the input data stream is demultiplexed into its original i and q data and then latched. a 4 ? and 8 ? clock multiplier enables the dac1205d750 to provide the appropriate internal clocks from the internal pll. the in ternal pll can be bypassed enabling the use of an external high frequency clock. the voltage regulator enables adjustment of the output full-scale current. 2. features and benefits dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating rev. 3 ? 7 june 2011 product data sheet ? dual 12-bit resolution ? imd3: 74 dbc; f s = 737.28 msps; f o = 140 mhz ? 750 msps maximum update rate ? acpr: 69 dbc; 2-carrier wcdma; f s = 737.28 msps; f o =153.6mhz ? selectable 4 ? or 8 ? interpolation filters ? typical 1.2 w power dissipation at 4 ? interpolation, pll off and 740 msps ? input data rate up to 185 msps ? power-down and sleep modes ? very low noise cap-free integrated pll ? differential scalable output current from 1.6 ma to 22 ma ? 32-bit programmable nco frequency ? on-chip 1.25 v reference ? dual port or interleaved data modes ? external analog offset control (10-bit auxiliary dacs) ? 1.8 v and 3.3 v power supplies ? internal digital offset control ? lvds compatible clock ? inverse x / (sin x) function ? two?s complement or binary offset data format ? fully compatible spi port ? 1.8 v/3.3 v cmos input data buffers ? industrial temperature range from ? 40 ? c to +85 ? c
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 2 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 3. applications ? wireless infrastructure: lte, wim ax, gsm, cdma, wcdma, td-scdma ? communication: lmds/mmds, point-to-point ? direct digital synthesis (dds) ? broadband wireless systems ? digital radio links ? instrumentation ? automated test equipment (ate) 4. ordering information table 1. ordering information type number package name description version DAC1205D750HW htqfp100 plastic thermal enhanced thin quad flat package; 100 leads; body 14 ? 14 ? 1 mm; exposed die pad sot638-1
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 3 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 5. block diagram fig 1. block diagram 001aam193 dac1205d750 fir1 2 2 fir1 fir2 2 2 fir2 fir3 2 2 fir3 nco cos sin 62 66 12 63 65 64 clock generator/pll complex modulator latch q latch i clkp reset_n syncp dac auxiliary dac auxiliary dac dac reference bandgap offset control 10-bit gain control 10-bit offset control 10-bit gain control 10-bit offset control sclk scs_n sdio sdo clkn q0 to q11 dual port/ interleaved data modes i0 to i11 8 9 41, 42, 45 to 48, 51 to 56 18 to 25, 28 to 31 spi auxan gapout auxap ioutan vires ioutap ioutbn ioutbp auxbn auxbp 3 69 2 91 68 90 85 86 73 74 mixer + ++ + a b + ? mixer mixer mixer 13 syncn x sin x x sin x 12 12
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 4 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 6. pinning information 6.1 pinning fig 2. pin configuration DAC1205D750HW v dda(3v3) v dda(3v3) auxap auxbp auxan auxbn agnd agnd v dda(1v8) v dda(1v8) v dda(1v8) v dda(1v8) agnd gapout clkp vires clkn d.n.c. agnd reset_n v dda(1v8) scs_n n.c. sclk n.c. sdio tm1 sdo i9 q0 i8 q1 i7 q2 i6 q3 i5 tm0 v dd(io)(3v3) gndio i11 i10 q4 tm3 v dd(io)(3v3) gndio n.c. n.c. i4 q5 v ddd(1v8) agnd dgnd v dda(1v8) i3 agnd i2 v dda(1v8) i1 agnd i0 v dda(1v8) v ddd(1v8) agnd dgnd v dda(1v8) n.c. agnd n.c. ioutan v ddd(1v8) ioutap dgnd agnd tm2 n.c. dgnd agnd q9 v dda(1v8) q8 agnd q7 v dda(1v8) q6 agnd dgnd v ddd(1v8) q11/seliq q10 dgnd v ddd(1v8) v dda(1v8) ioutbp ioutbn agnd v dda(1v8) agnd v ddd(1v8) agnd 001aam194 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 56 55 54 53 52 51 15 16 17 18 19 61 60 59 58 57 26 27 28 29 30 31 32 33 34 35 36 37 38 39 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 81 80 79 78 77 76 40 41 42 43 44 86 85 84 83 82 agnd
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 5 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 6.2 pin description table 2. pin description symbol pin type [1] description v dda(3v3) 1 p analog supply voltage 3.3 v auxap 2 o auxiliary dac b output current auxan 3 o complementary auxiliary dac b output current agnd 4 g analog ground v dda(1v8) 5 p analog supply voltage 1.8 v v dda(1v8) 6 p analog supply voltage 1.8 v agnd 7 g analog ground clkp 8 i clock input clkn 9 i complement ary clock input agnd 10 g analog ground v dda(1v8) 11 p analog supply voltage 1.8 v syncp 12 o synchronous clock output syncn 13 o complementary synchronous clock output tm1 14 i/o test mode 1 (connected to dgnd) tm0 15 i/o test mode 0 (connected to dgnd) v dd(io)(3v3) 16 p input/output buffers supply voltage 3.3 v gndio 17 g input/output buffers ground i11 18 i i data input bit 11 (msb) i10 19 i i data input bit 10 i9 20 i i data input bit 9 i8 21 i i data input bit 8 i7 22 i i data input bit 7 i6 23 i i data input bit 6 i5 24 i i data input bit 5 i4 25 i i data input bit 4 v ddd(1v8) 26 p digital supply voltage 1.8 v dgnd 27 g digital ground i3 28 i i data input bit 3 i2 29 i i data input bit 2 i1 30 i i data input bit 1 i0 31 i i data input bit 0 (lsb) v ddd(1v8) 32 p digital supply voltage 1.8 v dgnd 33 g digital ground n.c. 34 not connected n.c. 35 not connected v ddd(1v8) 36 p digital supply voltage 1.8 v dgnd 37 g digital ground tm2 38 - test mode 2 (to connect to dgnd) dgnd 39 g digital ground
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 6 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating v ddd(1v8) 40 p digital supply voltage 1.8 v q11/seliq 41 i q data input bit 11 (msb)/select iq in interleaved mode q10 42 i q data input bit 10 dgnd 43 g digital ground v ddd(1v8) 44 p digital supply voltage 1.8 v q9 45 i q data input bit 9 q8 46 i q data input bit 8 q7 47 i q data input bit 7 q6 48 i q data input bit 6 dgnd 49 g digital ground v ddd(1v8) 50 p digital supply voltage 1.8 v q5 51 i q data input bit 5 q4 52 i q data input bit 4 q3 53 i q data input bit 3 q2 54 i q data input bit 2 q1 55 i q data input bit 1 q0 56 i q data input bit 0 (lsb) n.c. 57 i not connected n.c. 58 i not connected gndio 59 g input/output buffers ground v dd(io)(3v3) 60 p input/output buffers supply voltage 3.3 v tm3 61 i/o test mode 3 (to connect to dgnd) sdo 62 o spi data output sdio 63 i/o spi data input/output sclk 64 i spi clock input scs_n 65 i spi chip select (active low) reset_n 66 i general reset (active low) d.n.c. 67 - do not connect vires 68 i/o dac biasing resistor gapout 69 i/o bandgap input/output voltage v dda(1v8) 70 p analog supply voltage 1.8 v v dda(1v8) 71 p analog supply voltage 1.8 v agnd 72 g analog ground auxbn 73 o auxiliary dac b output current auxbp 74 o complementary auxiliary dac b output current v dda(3v3) 75 p analog supply voltage 3.3 v agnd 76 g analog ground v dda(1v8) 77 p analog supply voltage 1.8 v agnd 78 g analog ground v dda(1v8) 79 p analog supply voltage 1.8 v agnd 80 g analog ground table 2. pin description ?continued symbol pin type [1] description
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 7 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating [1] p = power supply g = ground i = input o = output. [2] h = heatsink (exposed die pad to be soldered) v dda(1v8) 81 p analog supply voltage 1.8 v agnd 82 g analog ground v dda(1v8) 83 p analog supply voltage 1.8 v agnd 84 g analog ground ioutbn 85 o complementary dac b output current ioutbp 86 o dac b output current agnd 87 g analog ground n.c. 88 - not connected agnd 89 g analog ground ioutap 90 o dac a output current ioutan 91 o complementary dac a output current agnd 92 g analog ground v dda(1v8) 93 p analog supply voltage 1.8 v agnd 94 g analog ground v dda(1v8) 95 p analog supply voltage 1.8 v agnd 96 g analog ground v dda(1v8) 97 p analog supply voltage 1.8 v agnd 98 g analog ground v dda(1v8) 99 p analog supply voltage 1.8 v agnd 100 g analog ground agnd h [2] g analog ground table 2. pin description ?continued symbol pin type [1] description
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 8 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 7. limiting values 8. thermal characteristics [1] in compliance with jedec test board, in free air. table 3. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd(io)(3v3) input/output supply voltage (3.3 v) ? 0.5 +4.6 v v dda(3v3) analog supply voltage (3.3 v) ? 0.5 +4.6 v v dda(1v8) analog supply voltage (1.8 v) ? 0.5 +3.0 v v ddd(1v8) digital supply voltage (1.8 v) ? 0.5 +3.0 v v i input voltage pins clkp, clkn, vires and gapout referenced to pin agnd ? 0.5 +3.0 v pins i11 to i0, q11 to q0, sdo, sdio, sclk, scs_n and reset_n re ferenced to gndio ? 0.5 +4.6 v v o output voltage pins ioutap, ioutan, ioutbp, ioutbn, auxap, auxan, auxbp and auxbn referenced to pin agnd ? 0.5 +4.6 v pins syncp and syncn referenced to pin agnd ? 0.5 +3.0 v t stg storage temperature ? 55 +150 ? c t amb ambient temperature ? 40 +85 ? c t j junction temperature - 125 ? c table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 19.8 k/w r th(j-c) thermal resistance fr om junction to case [1] 7.7 k/w
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 9 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 9. characteristics table 5. characteristics v dda(1v8) =v ddd(1v8) = 1.8 v; v dda(3v3) =v dd(io)(3v3) = 3.3 v; agnd, dgnd and g ndio shorted together; t amb = ? 40 ? cto+85 ? c; typical values measured at t amb =25 ? c; r l = 50 ? differential; i o(fs) = 20 ma; pll off unless otherwise specified. symbol parameter conditions test [1] min typ max unit v dd(io)(3v3) input/output supply voltage (3.3 v) i3.03.33.6v v dda(3v3) analog supply voltage (3.3 v) i3.03.33.6v v dda(1v8) analog supply voltage (1.8 v) i1.71.81.9v v ddd(1v8) digital supply voltage (1.8 v) i 1.7 1.8 1.9 v i dd(io)(3v3) input/output supply current (3.3 v) f o =19mhz; f s =740msps; 4 ? interpolation; nco on i-0.50.7ma i dda(3v3) analog supply current (3.3 v) f o =19mhz; f s =740msps; 4 ? interpolation; nco on i - 44 50 ma i ddd(1v8) digital supply current (1.8 v) f o =19mhz; f s =740msps; 4 ? interpolation; nco on i - 181 210 ma i dda(1v8) analog supply current (1.8 v) f o =19mhz; f s =740msps; 4 ? interpolation; nco on i - 360 391 ma i ddd digital supply current for x / (sin x) function only i-70-ma p tot total power dissipation f o =19mhz; f s = 740 msps 4 ? interpolation nco off; dac b off c - 0.74 - w nco off c - 0.89 - w nco on; all v dd c - 1.12 1.32 w 8 ? interpolation nco on i - 1.11 - w power-down mode: full power-down; all v dd i - 0.03 0.06 w dac a and dac b sleep mode; nco on i - 0.63 - w
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 10 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating clock inputs (clkp and clkn) [2] v i input voltage clkn ? v gpd ? <50mv or clkp c [3] 825 - 1575 mv v idth input differential threshold voltage ? v gpd ? < 50 mv c [3] ? 100 - +100 mv r i input resistance d - 10 - m ? c i input capacitance d - 0.5 - pf clock outputs (syncp and syncn) v o(cm) common-mode output voltage c-v dda(1v8) ? 0.3 -v v o(dif) differential output voltage c - 1.2 - v r o output resistance d - 80 - ? digital inputs (i0 to i11, q0 to q11) v il low-level input voltage c gndio - 0.8 v v ih high-level input voltage c 1.6 - v dd(io)(3v3) v i il low-level input current v il =0.8v i - 60 - ? a i ih high-level input current v ih =2.3v i - 80 - ? a digital inputs (sdo, sdio, sclk, scs_n and reset_n) v il low-level input voltage c gndio - 1.0 v v ih high-level input voltage c 2.3 - v dd(io)(3v3) v i il low-level input current v il =1.0v i - 20 - na i ih high-level input current v ih =2.3v i - 20 - na analog outputs (ioutap, ioutan, ioutbp and ioutbn) i o(fs) full-scale output current register value = 00h c - 1.6 - ma default register c - 20 - ma v o output voltage compliance range c 1.8 - v dda(3v3) v r o output resistance d - 250 - k ? c o output capacitance d - 3 - pf ? e o offset error variation c - 6 - ppm/ ? c ? e g gain error variation c - 18 - ppm/ ? c reference voltage output (gapout) v o(ref) reference output voltage t amb = 25 ? c i 1.2 1.25 1.30 v ? v o(ref) reference output voltage variation c - 117 - ppm/ ? c i o(ref) reference output current external voltage 1.25 v d - 40 - ? a analog auxiliary outputs ( auxap, auxan, auxbp and auxbn) i o(aux) auxiliary output current differential outputs i - 2.2 - ma v o(aux) auxiliary output voltage compliance range c 0 - 2 v n dac(aux)mon o auxiliary dac monotonicity guaranteed d - 10 - bit table 5. characteristics ?continued v dda(1v8) =v ddd(1v8) = 1.8 v; v dda(3v3) =v dd(io)(3v3) = 3.3 v; agnd, dgnd and g ndio shorted together; t amb = ? 40 ? cto+85 ? c; typical values measured at t amb =25 ? c; r l = 50 ? differential; i o(fs) = 20 ma; pll off unless otherwise specified. symbol parameter conditions test [1] min typ max unit
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 11 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating input timing (see figure 10 ) f data data rate dual-port mode input c - - 185 mhz t w(clk) clk pulse width c 40 - 60 % t h(i) input hold time c 1.6 - - ns t su(i) input set-up time c 0.8 - - ns sync signal t d delay time f sync = f s / 4 c - 0.21 - ns f sync = f s / 8 c - 0.3 - ns variation c - 0.27 - ps/ ? c output timing f s sampling frequency c - - 750 msps t s settling time to ? 0.5 lsb d - 20 - ns nco frequency range f nco nco frequency register values 00000000h d - 0 - mhz ffffffffh d - 740 - mhz f step step frequency d - 0.172 - hz low-power nco frequency range f nco nco frequency register values 00000000h d - 0 - mhz f8000000h d - 716.875 - mhz f step step frequency d - 23.125 - mhz dynamic performance sfdr spurious-free dynamic range f s = 737.28 msps f data = 92.16 mhz; b = f data /2 f o = 4 mhz; 0 dbfs c - 77 - dbc f data = 184.32 mhz; b = f data /2 f o =19mhz; 0dbfs i - 74 - dbc f o =70mhz; 0dbfs c - 86 - dbc sfdr rbw restricted bandwidth spurious-free dynamic range f o = 153.6 mhz; 0 dbfs; f data = 184.32 mhz; f s = 737.28 msps b=20mhz c - 86 - dbc b=100mhz c - 80.5 - dbc b = 20 mhz; 8-tone; 500 khz spacing c-76- dbc table 5. characteristics ?continued v dda(1v8) =v ddd(1v8) = 1.8 v; v dda(3v3) =v dd(io)(3v3) = 3.3 v; agnd, dgnd and g ndio shorted together; t amb = ? 40 ? cto+85 ? c; typical values measured at t amb =25 ? c; r l = 50 ? differential; i o(fs) = 20 ma; pll off unless otherwise specified. symbol parameter conditions test [1] min typ max unit
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 12 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating [1] d = guaranteed by design; c = guaranteed by c haracterization; i = 100 % industrially tested. [2] clkp and clkn inputs are at differential lvds levels. an external differential resistor with a value of between 80 ? and 120 ? should be connected across the pins (see figure 8 ). [3] ? v gpd ? represents the ground potential difference voltage. this is the voltage that results from current flowing through the finite r esistance and the inductance between the receiver and the driver circuit ground voltages. [4] imd3 rejection with ? 6 dbfs/tone. imd3 third-order intermodulation distortion f data = 184.32 mhz; f s = 737.28 msps f o1 =95mhz; f o2 =97mhz c [4] -77 - dbc f o1 =137mhz; f o2 =143mhz c [4] -74 - dbc f o1 =152.5mhz; f o2 =153.5mhz i [4] -74 - dbc acpr adjacent channel power ratio f data = 184.32 mhz; f s = 737.28 msps; f o =96mhz 1-carrier; b = 5 mhz i - 73 - dbc 2-carrier; b = 10 mhz c - 70 - dbc 4-carrier; b = 20 mhz c - 68 - dbc f data = 184.32 mhz; f s = 737.28 msps; f o = 153.6 mhz 1-carrier; b = 5 mhz c - 72 - dbc 2-carrier; b = 10 mhz c - 69 - dbc 4-carrier; b = 20 mhz c - 66.5 - dbc nsd noise spectral density f data = 184.32 mhz; f s = 737.28 msps f o =19mhz;0dbfs c - ? 157 - dbfs/hz f o = 153.6 mhz; 0 dbfs; c- ? 155 - dbfs/hz f o = 153.6 mhz; ? 10 dbfs c- ? 157 - dbfs/hz table 5. characteristics ?continued v dda(1v8) =v ddd(1v8) = 1.8 v; v dda(3v3) =v dd(io)(3v3) = 3.3 v; agnd, dgnd and g ndio shorted together; t amb = ? 40 ? cto+85 ? c; typical values measured at t amb =25 ? c; r l = 50 ? differential; i o(fs) = 20 ma; pll off unless otherwise specified. symbol parameter conditions test [1] min typ max unit
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 13 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10. application information 10.1 general description the dac1205d750 is a dual 12-bit dac which operates at up to 750 msps. each dac consists of a segmented architecture, comprising a 6-bit thermometer sub-dac and an 6-bit binary weighted sub-dac. the input data rate of up to 185 mhz combined with the maximum output sampling rate of 750 msps make the dac1205d750 extremely flex ible in wide bandwidth and multi-carrier systems. the device?s quadrature modulator a nd 32-bit nco simplifies system frequency selection. this is also possible because the 4 ? and 8 ? interpolation filters remove undesired images. a sync signal is provided to synchronize data when the pll is in the off state. two modes are available for the digital input. in dual-port mode, each dac uses its own data input line. in interleaved mode, both dacs use the same data input line. the on-chip pll enables generation of the inte rnal clock signals for the digital circuitry and the dac from a low speed clock. the pll can be bypassed enabling the use of an external, high-speed clock. each dac generates two complementary current outputs on pins ioutap/ioutan and ioutbp/ioutbn. this provides a full-scale output current (i o(fs) ) up to 22 ma. an internal reference is available for the reference current which is externally adjustable using pin vires. there are also some em bedded features to prov ide an analog offset correction (auxiliary dacs) and digital offset control as well as fo r gain adjustment. all the functions can be set using the spi. the dac1205d750 operates at both 3.3 v and 1.8 v each of which has separate digital and analog power supplies. the digital input is 1.8 v and 3.3 v compliant and the clock input is lvds compliant. 10.2 serial peripheral interface 10.2.1 protocol description the dac1205d750 serial peripheral interface (spi) is a synchronous serial communication port allowing ea sy interfacing with many in dustry microprocessors. it provides access to the registers that define the operating modes of the chip in both write and read modes. this interface can be configured as a 3-wire ty pe (sdio as a bidirectional pin) or a 4-wire type (sdio and sdo as unidirectional pins, inpu t and output port respectively). in both configurations, sclk acts as the serial clo ck and scs_n acts as the serial chip select bar. each read/write operation is sequenced by the scs_n signal and enabled by a low assertion to drive the chip with 1 to 4 bytes, depending on the cont ent of the instruction byte (see ta b l e 7 ).
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 14 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating in table 7 n1 and n0 indicate the number of bytes transferred after the instruction byte. a0 to a4: indicate which register is being addressed. in the case of a multiple transfer, this address concerns the first register after which the next registers follow directly in a decreasing order according to table 9 ? register allocation map ? . 10.2.2 spi timing description the interface can operate at a frequency of up to 15 mhz. the spi timing is shown in figure 4 . r/w indicates the mode access, (see table 6 ) fig 3. spi protocol 001aaj812 reset_n scs_n sclk sdio sdo (optional) r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 table 6. read or write mode access description r/w description 0 write mode operation 1 read mode operation table 7. number of bytes transferred n1 n0 number of bytes 0 0 1 byte transferred 0 1 2 bytes transferred 1 0 3 bytes transferred 1 1 4 bytes transferred fig 4. spi timing diagram 001aaj813 50 % t w(reset_n) t su(scs_n) t su(sdio) t h(sdio) t h(scs_n) t w(sclk) 50 % reset_n scs_n sclk sdio 50 % 50 %
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 15 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating the spi timing characteristics are given in ta b l e 8 . 10.2.3 detailed descriptions of registers an overview of the details for all registers is provided in table 9 . table 8. spi timing characteristics symbol parameter min typ max unit f sclk sclk frequency - - 15 mhz t w(sclk) sclk pulse width 30 - - ns t su(scs_n) scs_n set-up time 20 - - ns t h(scs_n) scs_n hold time 20 - - ns t su(sdio) sdio set-up time 10 - - ns t h(sdio) sdio hold time 5 - - ns t w(reset_n) reset_n pulse width 30 - - ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 16 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating table 9. register allocation map address register name r/w bit definition default dec hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin dec hex 0 00h common r/w 3w_spi spi_rst clk_sel - mode_ sel coding ic_pd gap_pd 10000000 128 80 1 01h txcfg r/w nco_on nco_lp_ sel inv_sin_ sel modulation[2:0] interpolation[1:0] 10000111 135 87 2 02h pllcfg r/w pll_pd - pll_div_ pd pll_div[1:0] dac_clk_delay[1:0] dac_clk _pol 00010000 16 10 3 03h freqnco_lsb r/w freq_nco[7:0] 01100110 102 66 4 04h freqnco_lisb r/w freq_nco[15:8] 01100110 102 66 5 05h freqnco_uisb r/w freq _nco[23:16] 01100110 102 66 6 06h freqnco_msb r/w freq_ nco[31:24] 00100110 38 26 7 07h phinco_lsb r/w ph_nco[7:0] 00000000 0 00 8 08h phinco_msb r/w ph_nco[15:8] 00000000 0 00 9 09h dac_a_cfg_1 r/w dac_a_pd dac_a_ sleep dac_a_offset[4:0] - 00000000 0 00 10 0ah dac_a_cfg_2 r/w dac_a_gain_ coarse[1:0] dac_a_gain_fine[5:0] 01000000 64 40 11 0bh dac_a_cfg_3 r/w dac_a_gain_ coarse[3:2] dac_a_offset[10:5] 11000000 192 c0 12 0ch dac_b_cfg_1 r/w dac_b_pd dac_b_ sleep dac_b_offset[4:0] - 00000000 0 00 13 0dh dac_b_cfg_2 r/w dac_b_gain_ coarse[1:0] dac_b_gain_fine[5:0] 01000000 64 40 14 0eh dac_b_cfg_3 r/w dac_b_gain_ coarse[3:2] dac_b_offset[10:5] 11000000 192 c0 15 0fh dac_cfg r/w - minus_ 3db noise_ shper 00000000 0 00 16 10h sync_cfg r/w sync_div sync_sel - 00000000 0 00 26 1ah dac_a_aux_msb r/w aux_a[9:2] 10000000 128 80 27 1bh dac_a_aux_lsb r/w aux_a_pd - aux_a[1:0] 00000000 0 00 28 1ch dac_b_aux_msb r/w aux_b[9:2] 10000000 128 80 29 1dh dac_b_aux_lsb r/w aux_b_pd - aux_b[1:0] 00000000 0 00
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 17 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.2.4 detailed register descriptions please refer to ta b l e 9 for the register overview and relevant default values. in the following tables, all the values shown in bold are the default values. table 10. common register (a ddress 00h) bit description default settings are shown highlighted. bit symbol access value description 7 3w_spi r/w serial interface bus type 0 4 wire spi 1 3 wire spi 6 spi_rst r/w serial interface reset 0no reset 1 performs a reset on all registers except 00h 5 clk_sel r/w data input latch 0 at clk rising edge 1 at clk falling edge 4 - - - reserved 3 mode_sel r/w input data mode 0 dual port 1 interleaved 2 coding r/w coding 0binary 1 two?s compliment 1 ic_pd r/w power-down 0disabled 1 all circuits (digital and analog, except spi) are switched off 0 gap_pd r/w internal bandgap power-down 0 power-down disabled 1 internal bandgap references are switched off table 11. txcfg register (address 01h) bit description default settings are shown highlighted. bit symbol access value description 7 nco_on r/w nco 0 disabled (the nco phase is reset to 0) 1 enabled 6 nco_lp_sel r/w low-power nco 0 disabled 1 nco frequency and phase given by the five msbs of the registers 06h and 08h respectively 5 inv_sin_sel r/w x / (sin x) function 0 disabled 1 enabled
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 18 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 4 to 2 modulation[2:0] r/w modulation 000 dual dac: no modulation 001 positive upper single sideband up-conversion 010 positive lower single sideband up-conversion 011 negative upper single sideband up-conversion 100 negative lower single sideband up-conversion 1 to 0 interpolation[1:0] r/w interpolation 01 reserved 10 4 ? 11 8 ? table 12. pllcfg register (address 02h) bit description default settings are shown highlighted. bit symbol access value description pll on pll off 7 pll_pd r/w pll 0 switched on 1 switched off 6 - - reserved 5 pll_div_pd r/w pll divider undefined 0 switched on x 1 switched off x 4 to 3 pll_div[1:0] r/w pll divider factor digital clock delay 00 2 130 ps 01 4 280 ps 10 8 430 ps 11 x 580 ps 2 to 1 dac_clk_delay[1:0] r/w phase shift (f s ) undefined 00 0 ? x 01 120 ? x 10 240 ? x 0 dac_clk_pol r/w clock edge of dac (f s ) undefined 0 normal x 1 inverted x table 13. freqnco_lsb register (address 03h) bit description bit symbol access value description 7 to 0 freq_nco[7:0] r/w - lower 8 bits for the nco frequency setting table 11. txcfg register (address 01h) bit description ?continued default settings are shown highlighted. bit symbol access value description
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 19 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating table 14. freqnco_lisb register (address 04h) bit description bit symbol access value description 7 to 0 freq_nco[15:8] r/w - lower intermediate 8 bits for the nco frequency setting table 15. freqnco_uisb register (address 05h) bit description bit symbol access value description 7 to 0 freq_nco[23:16] r/w - upper intermediate 8 bits for the nco frequency setting table 16. freqnco_msb register (address 06h) bit description bit symbol access value description 7 to 0 freq_nco[31:24] r/w - most signif icant 8 bits for the nco frequency setting table 17. phinco_lsb register (address 07h) bit description bit symbol access value description 7 to 0 ph_nco[7:0] r/w - lower 8 bits for the nco phase setting table 18. phinco_msb register (address 08h) bit description bit symbol access value description 7 to 0 ph_nco[15:8] r/w - most significant 8 bits for the nco phase setting table 19. dac_a_cfg_1 register (a ddress 09h) bit description default settings are shown highlighted. bit symbol access value description 7 dac_a_pd r/w dac a power 0on 1off 6 dac_a_sleep r/w dac a sleep mode 0disabled 1 enabled 5 to 1 dac_a_offset[4:0] r/w - lower 5 bits for the dac a offset table 20. dac_a_cfg_2 register (a ddress 0ah) bit description bit symbol access value description 7 to 6 dac_a_gain_ coarse[1:0] r/w - lower 2 bits for the dac a gain setting for coarse adjustment 5 to 0 dac_a_gain_ fine[5:0] r/w - lower 6 bits for the dac a gain setting for fine adjustment
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 20 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating table 21. dac_a_cfg_3 register (a ddress 0bh) bit description bit symbol access value description 7 to 6 dac_a_gain_ coarse[3:2] r/w - most significant 2 bits for the dac a gain setting for coarse adjustment 5 to 0 dac_a_ offset[10:5] r/w - most significant 6 bits for the dac a offset table 22. dac_b_cfg_1 register (a ddress 0ch) bit description default settings are shown highlighted. bit symbol access value description 7 dac_b_pd r/w dac b power 0on 1off 6 dac_b_sleep r/w dac b sleep mode 0disabled 1 enabled 5 to 1 dac_b_offset[4:0] r/w - lower 5bits for the dac b offset table 23. dac_b_cfg_2 register (a ddress 0dh) bit description bit symbol access value description 7 to 6 dac_b_gain_ coarse[1:0] r/w - less significant 2 bits for the dac b gain setting for coarse adjustment 5 to 0 dac_b_gain_ fine[5:0] r/w - the 6 bits for the dac b gain setting for fine adjustment table 24. dac_b_cfg_3 register (address 0eh) bit description bit symbol access value description 7 to 6 dac_b_gain_ coarse[3:2] r/w - most significant 2 bits for the dac b gain setting for coarse adjustment 5 to 0 dac_b_ offset[10:5] r/w - most significant 6 bits for the dac b offset table 25. dac_cfg register (add ress 0fh) bit description default settings are shown highlighted. bit symbol access value description 7 to 2 - - - reserved 1 minus_3db r/w nco gain 0unity 1 ? 3 db 0 noise_shper r/w noise shaper 0 disabled 1 enabled
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 21 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating table 26. sync_cfg register (address 10h) bit description default settings are shown highlighted. bit symbol access value description 7 sync_div r/w f s divided by 04 18 6 sync_sel r/w sync selection 0disabled 1 enabled 5 to 0 - - - reserved table 27. dac_a_aux_msb register (address 1ah) bit description bit symbol access value description 7 to 0 aux_a[9:2] r/w - most significant 8 bits for the auxiliary dac a table 28. dac_a_aux_lsb register (address 1bh) bit description default settings are shown highlighted. bit symbol access value description 7 aux_a_pd r/w auxiliary dac a power 0on 1off 6 to 1 - - reserved 1 to 0 aux_a[1:0] r/w lower 2 bi ts for the auxiliary dac a table 29. dac_b_aux_msb register (address 1ch) bit description bit symbol access value description 7 to 0 aux_b[9:2] r/w - most significant 8 bits for the auxiliary dac b table 30. dac_b_aux_lsb register (address 1dh) bit description default settings are shown highlighted. bit symbol access value description 7 aux_b_pd r/w auxiliary dac b power 0on 1off 6 to 1 - - reserved 1 to 0 aux_b[1:0] r/w lower 2-bits for the auxiliary dac b
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 22 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.2.5 recommended configuration it is recommended that the following additional settings are used to obtain optimum performance at up to 750 msps 10.3 input data the setting applied to mode_sel (register 00h[3]; see table 10 on page 17 ) defines whether the dac1205d750 operates in the dual-port mode or in interleaved mode (see ta b l e 3 2 ). 10.3.1 dual-port mode the data input for dual-port mode operation is shown in figure 5 ? dual-port mode ? . each dac has its own independent data input. the data enters the input latch on the rising edge of the internal clock signal and is transferred to the dac latch. 10.3.2 interleaved mode the data input for the interleaved mode operation is illustrated in figure 6 ? interleaved mode operation ? . table 31. recommended configuration address value dec hex bin dec hex 17 11h 00001010 10 0ah 19 13h 01101100 108 6ch 20 14h 01101100 108 6ch table 32. mode selection bit 3 setting function i11 to i0 q11 to q0 pin 41 0 dual port mode active active q11 1 interleaved mode active off seliq fig 5. dual-port mode 001aam195 latch i 2 2 2 i11 to i0 fir 1 fir 1 fir 2 fir 2 fir 3 fir 3 latch q 2 2 2 q11 to q0
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 23 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating in interleaved mode, both dacs use the same data input at twice the dual-port mode frequency. data enters the latch on the rising edge of the internal clock signal. the data is sent to either latch i or latch q, depending on the seliq signal. the seliq input (pin 41 ) allows the synchronization of th e internally demultiplexed i and q channels; see figure 7 . the seliq signal can be either synchronous or asynchronous (single rising edge, single pulse). the first data following the seliq risi ng edge is sent in channel i and following data is sent in channel q. after this, da ta is distributed alternately between these channels. fig 6. interleaved mode operation clk dig = internal digital clock fig 7. interleaved mode timing (8x in terpolation, latch on rising edge) 001aam196 latch i 2 2 2 fir 1 fir 1 fir 2 fir 2 fir 3 fir 3 latch q 2 2 2 i11 to i0 q11/seliq 001aaj814 n in seliq (synchronous alternative) seliq (asynchronous alternative 1) seliq (asynchronous alternative 2) clk dig latch i output latch q output xx n n + 2 n + 1 n + 2 n + 3 n + 4 n + 5 xx n + 1 n + 3
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 24 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.4 input clock the dac1205d750 can operate at the following clock frequencies: pll on: up to 185 mhz in dual-port mode and up to 370 mhz in interleaved mode pll off: up to 750 mhz the input clock is lvds compliant (see figure 8 ) but it can also be interfaced with cml differential sine wave signal (see figure 9 ). 10.5 timing the dac1205d750 can operate at a sampling frequency (f s ) up to 750 msps with an input data rate (f data ) up to 185 mhz. when using the intern al pll, the input data is referenced to the clk signal. when the internal pll is bypassed, the sync signal is used as a reference. the input timing in the second case is shown in figure 10 . fig 8. lvds clock configuration fig 9. interfacing cml to lvds 001aah021 100 lvds clkinp clkinn lvds z diff = 100 001aah020 55 55 1.1 k 2.2 k 100 nf cml 100 nf 100 nf clkinp lvds clkinn agnd v dda(1v8) 1 k z diff = 100
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 25 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.5.1 timing when using the internal pll (pll on) in table 33 , the links between internal and external clocking are defined. the setting applied to pll_div[1:0] (register 02h[4:3]; see table 9 ? register allocation map ? ) allows the frequency between the digital part and the dac core to be adjusted. the settings applied to dac_clk_delay[1: 0] (register 02h[2:1]) and dac_clk_pol (register 02h[0]), allow adjustment of the ph ase and polarity of the sampling clock. this occurs at the input of the dac core and depends mainly on the sampling frequency. some examples are given in ta b l e 3 4 . 10.5.2 timing when using an external pll (pll off) it is recommended that a delay of 280 ps is used on the internal digital clock (clk dig ) to obtain optimum device performance up to750 msps. 10.6 fir filters the dac1205d750 integrates three selectab le finite impulse response (fir) filters which enables the device to use 4 ? or 8 ? interpolation rates. all three interpolation filters have a stop-band attenuation of at least 80 dbc and a pass-band ripple of less than 0.0005 db. the coefficients of the interpolation filters are given in table 36 ? interpolation filter coefficients ? . fig 10. input timing diagram when internal pll bypassed (off) 001aam197 n t su(i) 90 % 50 % 90 % i11 to i0/ q11 to q0 sync (syncp ? syncn) t h(i) n + 1 n + 2 table 33. frequencies mode clk input (mhz) input data rate (mhz) interpolation update rate (msps) pll_div[1:0] dual port 185 185 4 ? 740 01 (/ 4) dual port 92.5 92.5 8 ? 740 10 (/ 8) interleaved 370 370 4 ? 740 00 (/ 2) interleaved 185 185 8 ? 740 01 (/ 4) table 34. sample clock phase and polarity examples mode input data rate (mhz) interpolation update rate (msps) dac_clk_ delay [1:0] dac_clk_ pol dual port 92.5 4 ? 370 01 0 dual port 92.5 8 ? 740 01 0 table 35. optimum external pll timing settings address register name value dec hex digital clock delay bin dec hex 2 02h pllcfg 280 ps 10001000 136 88h
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 26 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.7 quadrature modulator and numerica lly controlled oscillator (nco) the quadrature modulator allows the 12-bit i and q-data to be mixed with the carrier signal generated by the nco. the frequency of the nu merically controlled oscillator (nco ) is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion. table 36. interpolation filter coefficients first interpolation filter second interpolation filter third interpolation filter lower upper value lower upper value lower upper value h(1) h(55) ? 4 h(1) h(23) ? 2 h(1) h(15) ? 39 h(2) h(54) 0 h(2) h(22) 0 h(2) h(14) 0 h(3) h(53) 13 h(3) h(21) 17 h(3) h(13) 273 h(4) h(52) 0 h(4) h(20) 0 h(4) h(12) 0 h(5) h(51) ? 34 h(5) h(19) ? 75 h(5) h(11) ? 1102 h(6) h(50) 0 h(6) h(18) 0 h(6) h(10) 0 h(7) h(49) 72 h(7) h(17) 238 h(7) h(9) 4964 h(8) h(48) 0 h(8) h(16) 0 h(8) - 8192 h(9) h(47) ? 138 h(9) h(15) ? 660 - - - h(10) h(46) 0 h(10) h(14) 0 - - - h(11) h(45) 245 h(11) h(13) 2530 - - - h(12) h(44) 0 h(12) - 4096 - - - h(13) h(43) ? 408------ h(14)h(42)0------ h(15) h(41) 650 - - - - - - h(16)h(40)0------ h(17) h(39) ? 1003------ h(18)h(38)0------ h(19) h(37) 1521 - - - - - - h(20)h(36)0------ h(21) h(35) ? 2315------ h(22)h(34)0------ h(23) h(33) 3671 - - - - - - h(24)h(32)0------ h(25) h(31) ? 6642------ h(26)h(30)0------ h(27) h(29) 20756 - - - - - - h(28) 32768------
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 27 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.7.1 nco in 32-bit when using the nco, the frequency can be set by the four registers freqnco_lsb, freqnco_lisb, freqnco_uisb a nd freqnco_msb over 32 bits. the frequency for the nco in 32-bit is calculated as follows: (1) where m is the decimal representation of freq_nco[31:0]. the phase of the nco can be set from 0 ? to 360 ? by both registers phinco_lsb and phinco_msb over 16 bits. 10.7.2 low-power nco when using the low-power nco, the frequency can be set by the 5 msb of register freqnco_msb. the frequency for the low-power nco is calculated as follows: (2) where m is the decimal representation of freq_nco[31:27]. the phase of the low-power nco can be set by the 5 msb of the register phinco_msb. 10.7.3 minus_3db function during normal use, a full-scale pattern will al so be full scale at the output of the dac. nevertheless, when the i and q data are simultaneously close to full scale, some clipping can occur and the minus_3db function can be used to reduce the gain by 3 db in the modulator. this is to keep a full-scale range at the output of the dac without added interferers. 10.8 x / (sin x) due to the roll-off effect of th e dac, a selectable fir filter is inserted to compensate for the x / (sin x) effect. this filter introduces a dc loss of 3.4 db. the coefficients are represented in ta b l e 3 7 . f nco mf s ? 2 32 -------------- = f nco mf s ? 2 5 -------------- = table 37. inversion filter coefficients first interpolation filter lower upper value h(1) h(9) 2 h(2) h(8) ? 4 h(3) h(7) 10 h(4) h(6) ? 35 h(5) - 401
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 28 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.9 dac transfer function the full-scale output current for each dac is the sum of the two complementary current outputs: (3) the output current depends on the digital input data: (4) (5) the setting applied to coding (register 00h[2]; see table 9 ? register allocation map ? ) defines whether the dac1205d750 operates wit h a binary input or a two?s complement input. ta b l e 3 8 shows the output current as a fu nction of the input data, when i o(fs) = 20 ma. 10.10 full-scale current 10.10.1 regulation the dac1205d750 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 v reference to the gapout pin. it is recommended to decouple pin gapout using a 100 nf capacitor. the reference current is generated via an external resistor of 910 ? (1 %) connected to pin vires. a control amplifier sets the appropriate full-scale output current (i o(fs) ) for both dacs (see figure 11 ). table 38. dac transfer function data i11 to i0 and q11 to q0 ioutp (ma) ioutn (ma) binary two?s complement 0 0000 0000 0000 1000 0000 0000 0 20 ... ... ... ... ... 8192 1000 0000 0000 0000 0000 0000 10 10 ... ... ... ... ... 16383 1111 1111 1111 0111 1111 1111 20 0 i ofs ?? i ioutp i ioutn + = i ioutp i ofs ?? data 4095 --------------- - ?? ?? ? = i ioutn i ofs ?? 4095 data ? 4095 --------------------------------- - ?? ?? ? =
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 29 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating this configuration is optimum for temper ature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. the dac current can also be set by applying an external reference voltage to the non-inverting input pin gapout and disabling the internal bandgap reference voltage with gap_pd (register 00h[0]; see table 10 ? common register (address 00h) bit description ? ). 10.10.2 full-scale current adjustment the default full-scale current (i o(fs) ) is 20 ma but further adjustments can be made by the user to both dacs independently via the se rial interface from 1.6 ma to 22 ma, ? 10 %. the settings applied to da c_a_gain_coarse[3:0] (see table 20 ? dac_a_cfg_2 register (address 0ah) bit description ? and table 21 ? dac_a_cfg_3 register (address 0bh) bit description ? ) and to dac_b_gain coarse[3:0] (see table 23 ? dac_b_cfg_2 register (address 0dh) bit description ? and table 24 ? dac_b_cfg_3 register (address 0eh) bit description ? ) define the coarse variation of the full-scale current (see ta b l e 3 9 ). fig 11. internal reference configuration 001aaj816 ref. bandgap gapout vires dac current sources array agnd agnd 100 nf 909 (1 %) table 39. i o(fs) coarse adjustment default settings are shown highlighted. dac_gain_coarse[3:0] i o(fs) (ma) decimal binary 0 0000 1.6 1 0001 3.0 2 0010 4.4 3 0011 5.8 4 0100 7.2 5 0101 8.6 6011010.0 7011111.4 8 1000 12.8 9 1001 14.2 10 1010 15.6 11 1011 17.0 12 1100 18.5
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 30 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating the settings applied to dac_a_gain_fine[5:0] (see table 20 ? dac_a_cfg_2 register (address 0ah) bit description ? ) and to dac_b_gain_fine[5:0] (see table 23 ? dac_b_cfg_2 register (address 0dh) bit description ? ) define the fine variation of the full-scale current (see ta b l e 4 0 ). the coding of the fine gain adjustment is two?s complement. 10.11 digital offset adjustment when the dac1205d750 analog output is dc connected to the next stage, the digital offset correction can be used to adjust the common-mode level at the output of the dac. it adds an offset at the end of the digital part, just before the dac. the settings applied to dac_a_offset[11:0] (see table 19 ? dac_a_cfg_1 register (address 09h) bit description ? and table 21 ? dac_a_cfg_3 register (address 0bh) bit description ? ) and to ?dac_b_offset[11:0]? (see table 22 ? dac_b_cfg_1 register (address 0ch) bit description ? and table 24 ? dac_b_cfg_3 register (address 0eh) bit description ? ) define the range of variation of the digital offset (see table 41 ). 13 1101 20.0 14 1110 21.0 15 1111 22.0 table 40. i o(fs) fine adjustment default settings are shown highlighted. dac_gain_fine[5:0] delta i o(fs) decimal two?s complement ? 32 10 0000 ? 10.3 % ... ... ... 0 00 0000 0 ... ... ... 31 01 1111 +10 % table 39. i o(fs) coarse adjustment ?continued default settings are shown highlighted. dac_gain_coarse[3:0] i o(fs) (ma) decimal binary
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 31 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.12 analog output the dac1205d750 has two output channels each of which produces two complementary current outputs. these allow the even-order harmonics and noise to be reduced. the pins are ioutap/ioutan and ioutbp/ioutbn, respecti vely and need to be connected via a load resistor r l to the 3.3 v analog power supply (v dda(3v3) ). refer to figure 12 for the equivalent analog output circui t of one dac. this circuit consists of a parallel combination of nmos current so urces, and their associated switches, for each segment. the cascode source configuration increases the output impedance of the source, thus improving the dynamic performance of t he dac by introducing less distortion. the device can provide an output level of up to 2 v o(p-p) depending on the application, the following stages and the targeted performances. table 41. digital offset adjustment default settings are shown highlighted. dac_offset[11:0] offset applied decimal two?s complement ? 1024 100 0000 0000 ? 1024 ? 1023 100 0000 0001 ? 1023 ... ... ... ? 1 111 1111 1111 ? 1 0 000 0000 0000 0 +1 000 0000 0001 +1 ... ... ... +1022 011 1111 1110 +1022 +1023 011 1111 1111 +1023 fig 12. equivalen t analog output circuit (one dac) 001aah019 v dda(3v3) agnd ioutap/ioutbp ioutan/ioutbn r l r l agnd
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 32 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.13 auxiliary dacs the dac1205d750 in tegrates 2 auxiliary dacs that c an be used to compensate for any offset between the dac and the next stage in the transmission path. both auxiliary dacs have a re solution of 10-bit and are cu rrent sources (r eferenced to ground). (6) the output cu rrent depends on the auxiliary dac data: (7) (8) ta b l e 4 2 shows the output curr ent as a function of the auxiliary dac data. 10.14 output c onfiguration 10.14.1 basic output configuration the use of a differentially-coupled transf ormer output provides optimum distortion performance (see figure 13 ). in addition, it helps to match the impedance and provides electrical isolation. table 42. auxiliary dac transfer function default settings are shown highlighted. data aux[9:0] (binary) i auxp (ma) i auxn (ma) 0 00 0000 0000 0 2.2 ... ... ... ... 512 10 0000 0000 1.1 1.1 ... ... ... ... 1023 11 1111 1111 2.2 0 i oaux ?? i auxp i auxn + = auxp i oaux ?? aux 9:0 ?? 1023 ------------------------ - ?? ?? ? = auxn i oaux ?? (1023 a ? ux 9:0 ??? 1023 --------------------------------------------- ?? ?? ? = fig 13. 1 v o(p-p) differential output with transformer 001aaj817 50 50 50 ioutnp/ioutnn; v o(cm) = 2.8 v; v o(dif)(p-p) = 1 v ioutnp ioutnn 0 ma to 20 ma 2:1 0 ma to 20 ma v dda(3v3) v dda(3v3)
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 33 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating the dac1205d750 differential outputs can operate up to 2 v o(p-p) . in this configuration, it is recommended to connect the center tap of the transformer to a 62 ? resistor connected to the 3.3 v analog power supply, in order to adjust the dc common-mode to approximately 2.7 v (see figure 14 ). 10.14.2 dc interface to an analog quadrature modulator (aqm) when the system operation requires to keep the dc component of the spectrum, the dac1205d750 can use a dc interface to connec t to an aqm. in this case, the offset compensation for lo cancellation can be made with the use of the digital offset control in the dac. figure 15 provides an example of a c onnection to an aqm with a 1.7 v i(cm) common-mode input level. figure 16 provides an example of a c onnection to an aqm with a 3.3 v i(cm) common-mode input level. fig 14. 2 v o(p-p) differential output with transformer 001aaj818 50 100 100 ioutnp/ioutnn; v o(cm) = 2.7 v; v o(dif)(p-p) = 2 v ioutnp ioutnn 0 ma to 20 ma 4:1 0 ma to 20 ma v dda(3v3) 62 v dda(3v3) v dda(3v3) fig 15. an example of a dc interface to a 1.7 v i(cm) aqm 001aaj541 51.1 51.1 442 442 v dda(3v3) ioutnp ioutnn 0 ma to 20 ma bbp (1) ioutnp/ioutnn; v o(cm) = 2.67 v; v o(dif)(p-p) = 1.98 v (2) bbp/bbn; v i(cm) = 1.7 v; v i(dif)(p-p) = 1.26 v bbn aqm (v i(cm) = 1.7 v) 768 768 (1) (2)
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 34 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating the auxiliary dacs can be used to control the offset in a pr ecise range or with precise steps. figure 17 provides an example of a dc interfac e with the auxiliary dacs to an aqm with a 1.7 v i(cm) common-mode input level. figure 18 provides an example of a dc interfac e with the auxiliary dacs to an aqm with a 3.3 v i(cm) common-mode input level. fig 16. an example of a dc interface to a 3.3 v i(cm) aqm fig 17. an example of a dc interface to a 1.7 v i(cm) aqm using auxiliary dacs 001aaj542 54.9 54.9 237 237 v dda(3v3) ioutnp ioutnn bbp bbn aqm (v i(cm) = 3.3 v) 750 750 5 v 1.27 k 1.27 k (1) ioutnp/ioutnn; v o(cm) = 2.75 v; v o(dif)(p-p) = 1.97 v (2) bbp/bbn; v i(cm) = 3.3 v; v i(dif)(p-p) = 1.5 v (1) (2) 001aal655 51.1 51.1 442 442 v dda(3v3) ioutnp ioutnn 0 ma to 20 ma bbp bbn aqm (v i(cm) = 1.7 v) 698 698 51.1 51.1 auxnp auxnn 1.1 ma (typ.) (1) ioutnp/ioutnn; v o(cm) = 2.67 v; v o(dif)(p-p) = 1.94 v (2) bbp/bbn; v i(cm) = 1.7 v; v i(dif)(p-p) = 1.23 v; offset correction up to 50 mv (1) (2)
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 35 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating the constraints to adjust the interface are the output compliance range of the dac and the auxiliary dacs, the input common-mode leve l of the aqm, and t he range of offset correction. 10.14.3 ac interface to an analog quadrature modulator (aqm) when the aqm common-mode voltage is close to ground, the dac1205d750 must be ac-coupled and the auxiliary dacs are needed for offset correction. figure 19 provides an example of a c onnection to an aqm with a 0.5 v i(cm) common-mode input level using auxiliary dacs. fig 18. an example of a dc interface to a 3.3 v i(cm) aqm using auxiliary dacs 001aaj544 54.9 54.9 237 237 3.3 v ioutnp ioutnn auxnp auxnn bbp bbn aqm (v i(cm) = 3.3 v) 750 750 5 v 634 634 442 442 (1) ioutnp/ioutnn; v o(cm) = 2.75 v; v o(dif)(p-p) = 1.96 v (2) bbp/bbn; v i(cm) = 3.3 v; v i(dif)(p-p) = 1.5 v; offset correction up to 36 mv (1) (2)
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 36 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 10.15 power and grounding in order to obtain optimum performance, it is recommended that the 1.8 v analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with the ones on pins 6, 70, 79, 81, 83, 93, 95 and 97 on the top layer. to optimize the decoupling, the power supplies should be decoupled with the following ground pins: ? v ddd(1v8) : pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43 and pin 50 with 49. ? v dd(io)(3v3) : pin 16 with 17 and pin 60 with 59. ? v dda(1v8) : pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins 79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98. ? v dda(3v3) : pin 1 with 100 and pin 75 with 76. fig 19. an example of an ac interface to a 0.5 v i(cm) aqm using auxiliary dacs 001aaj589 66.5 66.5 10 nf v dda(3v3) ioutnp ioutnn 0 ma to 20 ma bbp bbn aqm (v i(cm) = 0.5 v) 2 k 2 k 5 v 174 174 34 34 auxnp auxnn 1.1 ma (typ.) 10 nf (1) ioutnp/ioutnn; v o(cm) = 2.65 v; v o(dif)(p-p) = 1.96 v (2) bbp/bbn; v i(cm) = 0.5 v; v i(dif)(p-p) = 1.96 v; offset correction up to 70 mv (1) (2)
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 37 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 11. package outline fig 20. package outline sot638-1 (htqfp100) unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) cely w v references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot638-1 ms-026 03-04-07 05-02-02 d (1) e (1) 14.1 13.9 16.15 15.85 d h e h 7.1 6.1 7.1 6.1 1.15 0.85 b p b p e e a 1 a l p detail x l (a 3 ) b 25 h d h e a 2 v m b d z d a c z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 10 mm scale htqfp100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad sot638-1 d h e h exposed die pad side
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 38 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 12. abbreviations table 43. abbreviations acronym description b bandwidth cdma code division multiple access cml current mode logic cmos complementary metal-oxide semiconductor dac digital-to-analog converter fir finite impulse response gsm global system for mobile communications if intermediate frequency imd3 third-order intermodulation distortion lisb lower intermediate significant byte lmds local multipoint distribution service lsb least significant bit lte long term evolution lvds low-voltage differential signaling mmds multichannel multipoint distribution service msb most significant bit nco numerically controlled oscillator nmos negative metal-oxide semiconductor pll phase-locked loop sfdr spurious-free dynamic range spi serial peripheral interface td-scdma time division-synchronous code division multiple access uisb upper intermediate significant byte wcdma wideband code division multiple access wimax worldwide interoperability for microwave access
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 39 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 13. glossary spurious-free dynamic range (sfdr): ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the largest spurious observed (harmonic and non-harmonic, excluding dc component) in the frequency domain. intermodulation distortion (imd): ? from a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products imd2 and imd3 (respectively, second and third-order components) are defined below. imd2 ? the ratio of the rms value of either tone to the rms value of the worst second order intermodulation product. imd3 ? the ratio of the rms value of either to ne to the rms value of the worst third order intermodulation product. restricted bandwidth spurious free dynamic range ? the ratio of the rms value of the reconstructed output sine wave to th e rms value of the noise, including the harmonics, in a given bandwidth centered around f offset . 14. revision history table 44. revision history document id release date data sheet status change notice supersedes dac1205d750 v.3 20110607 product data sheet - dac1205d750 v.2 modifications: ? section 2 ? features and benefits ? has been updated. ? low-level input voltage and high-level input voltage values for digital inputs (i0 to i13, q0 to q13) in table 5 ? characteristics ? have been updated. dac1205d750 v.2 20100910 product data sheet - dac1205d750 v.1 dac1205d750 v.1 20100802 product data sheet - -
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 40 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. 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nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
dac1205d750 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 7 june 2011 41 of 42 nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors dac1205d750 dual 12-bit dac, up to 750 msps; 4x and 8x interpolating ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 7 june 2011 document identifier: dac1205d750 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 thermal characteristics . . . . . . . . . . . . . . . . . . 8 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 application information. . . . . . . . . . . . . . . . . . 13 10.1 general description . . . . . . . . . . . . . . . . . . . . 13 10.2 serial peripheral interface. . . . . . . . . . . . . . . . 13 10.2.1 protocol description . . . . . . . . . . . . . . . . . . . . 13 10.2.2 spi timing description . . . . . . . . . . . . . . . . . . . 14 10.2.3 detailed descriptions of registers . . . . . . . . . . 15 10.2.4 detailed register descriptions . . . . . . . . . . . . . 17 10.2.5 recommended configuration . . . . . . . . . . . . . 22 10.3 input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.3.1 dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . 22 10.3.2 interleaved mode . . . . . . . . . . . . . . . . . . . . . . 22 10.4 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.5.1 timing when using the internal pll (pll on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.5.2 timing when using an external pll (pll off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.6 fir filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.7 quadrature modulator and numerically controlled oscillator (nco) . . . . . . . . . . . . . . 26 10.7.1 nco in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.7.2 low-power nco . . . . . . . . . . . . . . . . . . . . . . . 27 10.7.3 minus_3db function . . . . . . . . . . . . . . . . . . . . 27 10.8 x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.9 dac transfer function . . . . . . . . . . . . . . . . . . . 28 10.10 full-scale current . . . . . . . . . . . . . . . . . . . . . . 28 10.10.1 regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.10.2 full-scale current adjustment . . . . . . . . . . . . . 29 10.11 digital offset adjustment . . . . . . . . . . . . . . . . . 30 10.12 analog output . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.13 auxiliary dacs . . . . . . . . . . . . . . . . . . . . . . . . 32 10.14 output configuration . . . . . . . . . . . . . . . . . . . . 32 10.14.1 basic output configuration . . . . . . . . . . . . . . . 32 10.14.2 dc interface to an analog quadrature modulator (aqm) . . . . . . . . . . . . . . . . . . . . . . 33 10.14.3 ac interface to an analog quadrature modulator (aqm) . . . . . . . . . . . . . . . . . . . . . . 35 10.15 power and grounding. . . . . . . . . . . . . . . . . . . 36 11 package outline. . . . . . . . . . . . . . . . . . . . . . . . 37 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38 13 glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 39 15 legal information . . . . . . . . . . . . . . . . . . . . . . 40 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 40 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 40 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16 contact information . . . . . . . . . . . . . . . . . . . . 41 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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